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DS3065WP
3.3V, 8Mb, Nonvolatile SRAM with Clock
Detailed Description
The DS3065WP is an 8Mb (1024k x 8 bits), fully static,
nonvolatile (NV) memory similar in function and organiza-
tion to the DS1265W NV SRAM, but containing an RTC.
The device NV SRAM constantly monitors V CC for an out-
of-tolerance condition. When such a condition occurs,
the lithium energy source is automatically switched on
and write protection is unconditionally enabled to prevent
data corruption. There is no limit to the number of write
cycles that can be executed, and no additional support
circuitry is required for microprocessor interfacing. This
device can be used in place of SRAM, EEPROM, or flash
components.
User access to either the SRAM or the RTC registers is
accomplished with a byte-wide interface and discrete
control inputs, allowing for a direct interface to many
3.3V microprocessor devices.
The RTC contains a full-function clock/calendar with an
RTC alarm, battery monitor, and power monitor. RTC
registers contain century, year, month, date, day, hours,
minutes, and seconds data in a 24-hour BCD format.
Corrections for day of the month and leap year are made
automatically.
The RTC registers are double-buffered into an internal
and external set. The user has direct access to the exter-
nal set. Clock/calendar updates to the external set of
registers can be disabled and enabled to allow the user
to access static data. Assuming the internal oscillator is
on, the internal registers are continually updated, regard-
less of the state of the external registers, assuring that
accurate RTC information is always maintained.
The device constantly monitors the voltage of the internal
battery. The battery-low flag (BLF) in the RTC FLAGS
read. Should a 1 ever be present, the battery voltage is
below ~ 2V and the contents of the clock and SRAM are
questionable.
The device module is constructed on a standard 34-pin
PowerCap substrate.
SRAM Read Mode
The device executes an SRAM read cycle whenever CS
(RTC chip select) and WE (write enable) are inactive
(high) and CE (SRAM chip enable) is active (low). The
unique address specified by the 20 address inputs
(A0–A19) defines which of the 1,048,576 bytes of SRAM
data is to be accessed. Valid data is available to the
eight data-output drivers within t ACC (access time) after
the last address input signal is stable, provided that CE
and OE (output enable) access times are also satisfied.
If CE and OE access times are not satisfied, data access
must be measured from the later occurring signal ( CE or
OE ), and the limiting parameter is either t CO for CE or
t OE for OE rather than address access.
SRAM Write Mode
The device executes an SRAM write cycle whenever CS
is inactive (high) and the CE and WE signals are active
(low) after address inputs are stable. The later-occurring
falling edge of CE or WE determines the start of the write
cycle. The write cycle is terminated by the earlier rising
edge of CE or WE . All address inputs must be kept valid
throughout the write cycle. WE must return to the high
state for a minimum recovery time (t WR ) before another
cycle can be initiated. The CS and OE control signal
should be kept inactive (high) during SRAM write cycles
to avoid bus contention. However, if the output drivers
have been enabled ( CE and OE active), WE disables the
outputs in t ODW from its falling edge.
register is not writable and should always be a 0 when
Table 1. RTC/Memory Operational Truth Table
CS
0
0
0
1
1
1
1
0
WE
1
1
0
1
1
0
X
X
CE
1
1
1
0
0
0
1
0
OE
0
1
X
0
1
X
X
X
MODE
RTC Read
RTC Read
RTC Write
SRAM Read
SRAM Read
SRAM Write
Standby
Invalid
(see Figure 2)
ICC
Active
Active
Active
Active
Active
Active
Standby
Active
OUTPUTS
Active
High Impedance
High Impedance
Active
High Impedance
High Impedance
High Impedance
Invalid
X = Don’t care.
10
Maxim Integrated
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